CONVOLVE: Seamless design of Smart Edge Processors
CONVOLVE enforces Europe’s position in the design and development of smart edge-processors, such that it can become a dominant player in the global edge processing market. This requires a holistic approach that will address the whole design stack from application, model, compiler, system architecture, micro architecture, circuit and device.
The project consortium consists of 18 partners from academia and industry with strong complementary competencies in different levels of design hierarchy:
Technische Universiteit Eindhoven, Eidgenössische Technische Hochschule Zürich, Friedrich Miescher Institute for Biomedical Research Foundation,Thales Alenia Space, Technische Universiteit Delft, Katholieke Universiteit Leuven,Bosch,NXP,GN, Ruhr-Universität Bochum, The University of Manchester, The University of Edinburgh, Universidad de Murcia, Universite Internationale de Rabat, ViNotion, CognitiveIC, Institute of Communication & Computer Systems, conferderation of laboratories for AI Research in Europe
A novel hardware & software platform to revolutionise artificial intelligence at the edge
Integrating AI algorithms into edge computing enables edge devices to make predictions and inferences based on incoming data. The inference at the edge market is experiencing significant growth. In this context, the EIC-funded Axelera® Europa project proposes a solution comprising hardware and software platforms optimised for inference at the edge.
This solution offers accelerated processing for the latest generation of neural network models in areas such as computer vision, natural language processing and generative AI. The hardware platform is available in multiple versions (form factors) to facilitate adoption, ranging from a single device in an embedded system to multiple instances on cards within an edge data centre.
DARE consortium: Supporting the EuroHPC Joint Undertaking (JU) in its mission to establish a world-class supercomputing ecosystem in Europe.
Axelera AI is proud to be part of the DARE consortium. DARE is committed to advancing the design and development of European processors, accelerators, and related technologies, enabling extreme-scale, high-performance computing (HPC) and emerging applications.
As a key contributor, Axelera AI brings its Titania® technology, designed for scalable, energy-efficient, and highly resilient HPC and data center solutions. This collaboration aligns with EuroHPC JU’s goal of building an integrated infrastructure for supercomputing and quantum computing, fostering European technological sovereignty and innovation in AI-driven acceleration.
RIGOLETTO: Powering Automotive Intelligence on RISC-V
RIGOLETTO is a three-year Chips JU project (2025–2028) building a next-gen automotive computing platform on open RISC-V. The pan-European consortium—led by Infineon and including Axelera, NXP, STMicroelectronics, Bosch, and top research labs—will deliver processor cores, AI/ML accelerators, and key IP for centralized vehicle control.
Axelera brings the “AI muscle” for RISC-V chips in cars:
We are co-designing new on-chip math features for efficient neural network processing, validating ultra-compact number formats for energy savings, and applying digital in-memory computing to minimise data movement—enabling fast, low-power vision and ADAS. Our work seeds scalable AI cores and interfaces for future automotive SoCs.
“Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or the Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them.”
